Serial Wire Debug (SWD) is an alternative to JTAG that uses a 2-pin interface (SWDIO and SWCLK) to provide debug access to ARM Cortex microcontrollers. It is part of the ARM CoreSight debug architecture and is more pin-efficient than JTAG, making it ideal for space-constrained designs.
The SWD interface provides the same capabilities as the 4/5-pin JTAG (boundary scan, flash programming, debugging), but with fewer pins. SWO (Serial Wire Output) adds trace capabilities, allowing developers to output debug information over a single trace pin.
* Pins marked with GND* are Ground on most debuggers but may be used for other purposes in some special adapters.
| Pin | Name | Description |
|---|---|---|
| 1 | VTref | Target reference voltage. Used to check if target has power and as reference for input comparators. |
| 2 | NC | Not connected. Reserved for compatibility. |
| 3 | NC | Not used by J-Link in SWD mode. May be connected to nTRST if device is also accessed via JTAG. |
| 4 | GND | Ground |
| 5 | NC | Not used by J-Link in SWD mode. May be connected to TDI if device is also accessed via JTAG. |
| 6 | GND | Ground |
| 7 | SWDIO | Single bi-directional data pin for SWD interface. |
| 8 | GND | Ground |
| 9 | SWCLK | Clock signal for SWD interface. |
| 10 | GND | Ground |
| 11 | NC | Not used by J-Link in SWD mode. May be connected to RTCK if device is also accessed via JTAG. |
| 12 | GND | Ground |
| 13 | SWO | Serial Wire Output trace port. Optional, not required for SWD communication. |
| 14 | GND* | Ground |
| 15 | nRESET | Target CPU reset signal (active low). |
| 16 | GND* | Ground |
| 17 | NC | Not connected in J-Link. |
| 18 | GND* | Ground |
| 19 | 5V-Supply | Used to supply power to some evaluation boards. |
| 20 | GND* | Ground |